Alif Semiconductor /AE722F80F55D5LS_CM55_HP_View /LPGPIO /GPIO_INT_BOTHEDGE

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Interpret as GPIO_INT_BOTHEDGE

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Val_0x0)GPIO_INT_BOTHEDGE

GPIO_INT_BOTHEDGE=Val_0x0

Description

GPIO Port Interrupt Both Edge Type Register

Fields

GPIO_INT_BOTHEDGE

Writing a 1 to a bit of this field enables the generation of interrupts on both the Rising edge and the Falling edge of an external input signal. The values programmed in the registers GPIO_INTTYPE_LEVEL and GPIO_INT_POLARITY for this particular bit are not considered when the corresponding bit of this field is set to 1. Writing a 0 to a bit of this field makes the interrupt type to depend on the value of the corresponding bits in the GPIO_INTTYPE_LEVEL and GPIO_INT_POLARITY registers.

0 (Val_0x0): Single edge sensitive

1 (Val_0x1): Both edge sensitive

Links

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